1. Field of the Invention
The present invention relates to a data processing apparatus and method for generating the data of an object program for a parallel operation apparatus, a computer program for the data processing apparatus, an information storage medium storing the data of the computer program, a parallel operation apparatus operable according to the object program, and a data processing system which comprises the parallel operation apparatus and the data processing apparatus.
2. Description of the Related Art
Products called CPU (Central Processing Unit) and MPU (Micro-Processor Unit) are used in the art as processor units capable of freely performing various data processing processes.
In a data processing system using such a processor unit, various object codes descriptive of a plurality of operation instructions and various processing data are stored in a memory device, and the processing unit sequentially reads operation instructions and processing data from the memory device and successively executes a plurality of data processing processes.
While one processor unit is capable of performing various data processing processes, since the processor unit needs to carry out the processing processes successively in sequence, and also need to read operation instructions from the memory device for the respective processing processes, it is difficult for the processor unit to execute complex processing processes at a high speed.
If there is only one data processing process to be carried out and if a logic circuit for carrying out the data processing process is hardware-implemented, then a processor unit would not be required to read a plurality of operation instructions sequentially from a memory device and execute a plurality of data processing processes successively in sequence. Therefore, a complex data processing process can be performed at a high speed, though only one data processing process can be executed.
Stated otherwise, a data processing system wherein object codes are freely changeable is capable of performing various data processing processes, but finds it difficult to carry out data processing processes at a high speed because it has a fixed hardware arrangement. On the other hand, a hardware-implemented logic circuit can carry out a data processing process at a high speed, but can execute only one data processing process as no object code can be changed.
To solve the above problem, the present applicant has devised, and filed a patent application on, a parallel operation apparatus as a processor unit whose hardware arrangement changes depending on software. The parallel operation apparatus has been disclosed in Japanese laid-open patent publication No. 2001-236385. The disclosed parallel operation apparatus has a matrix of many small-scale processing circuits and interconnection circuits and a state manager connected parallel to the matrix.
The processing circuits perform respective data processing processes individually according to operation instructions based on individual data settings, and the interconnection circuits individually control connections between the processing circuits according to operation instructions based on individual data settings. The parallel operation apparatus can perform various data processing processes because it changes the hardware arrangement by changing operation instructions for the processing circuits and the interconnection circuits, and can execute data processing processes at a high speed because the many small-scale processing circuits as hardware circuits perform simple data processing processes parallel to each other.
Since the state manager successively switches contexts made up of operation instructions for the processing circuits and the interconnection circuits in respective operation cycles according to object codes, the parallel operation apparatus can parallel processing processes consecutively according to the object codes.
Parallel operation apparatus in which contexts are successively switched in a plurality of cycles are disclosed in “Introduction to the Configurable, Highly Parallel Computer” published by Lawrence Snyder of Purdue University in IEEE Computer, vol. 15, No. 1, January 1982, pp. 47–56, Japanese laid-open patent publications Nos. 2000-138579, 2000-224025, 2000-232354, and 2000-232162 based on patent applications filed by the present applicant.
In the above parallel operation apparatus, since a state manager switches contexts contained in object codes successively in respective operation cycles, a plurality of processing circuits and a plurality of interconnection circuits which are connected in a matrix operate parallel to each other in the operation cycles according to the contexts.
However, the above parallel operation apparatus are basically different from conventional CPUs as to both structure and operation. Therefore, the parallel operation apparatus are unable to simply generate object codes from source codes according to a conventional method. There has been no technique available in the art so far for generating object codes from source codes for the above parallel operation apparatus.